Forum Discussion
Honored ContributorHelp wanted, C to state machines, or any alternatives.
Hi,
i need help, im a student doing my project. i run the Matlab simulation perfectly in matlab using the simulink models. i need to control 3 phase switches using the altera deo nano FPGA. is there a way can i convert the codings into state machines? thank u very much. function [sw_a, sw_b, sw_c, aa, bb, cc] = DLL(Ia_error, Ib_error, Ic_error, hysteresis_band, a, b, c) % sw_a, sw_b and sw_c are the switching gate signals h = hysteresis_band; % Phase a: if (Ia_error >= h) sw_a = 1; elseif (Ia_error <= -h) sw_a = 0; else sw_a = a; end aa = sw_a; % Phase b: if (Ib_error >= h) sw_b = 1; elseif (Ib_error <= -h) sw_b = 0; else sw_b = b; end bb = sw_b; % Phase c: if (Ic_error >= h) sw_c = 1; elseif (Ic_error <= -h) sw_c = 0; else sw_c = c; end cc = sw_c; end5 Replies
Altera_ForumYou probably should begin by gaining a basic understanding of what HDL design is all about, either VHDL or System Verilog. The fundamental design space between C and HDL is different. C distributes an algorithm in time using memory. HDL distributes an algorithm in time and space using all available FPGA resources, which can be completely parallel, serial, or a combination of both in terms of the algorithm. With that said, having done what you are trying to do, I would suggest separate processes for generating the error signal, then another process for determination of whether you need to switch the phase leg high or low. The sequential control of the data from these processes could be done with simply hardware handshaking or more elegantly a finite state machine.
- Altera_Forum
ive done some research regards the FSM. it can be easily convert the state machines into VHDL codings using the Quartus II software. theres a video on youtube showing how it is being done. But my problem, i cannot relate the ogic of the if else statement into state machines. how do i go about starting? thank you.
- Altera_Forum
The C code you show in your post doesn't have any states so it would be hard to convert it to a state machine. It can be translated in VHDL using simple combinational statements.
- Altera_Forum
Your code would map to three (independent) case statements in verilog/VHDL based on the inputs into your function. So is there something sequencing the calls to your C function because like Daixiwn said there are no states in the code you posted.
- Altera_Forum
MathWorks provides the product Stateflow to build state machines and flow charts. The 3 phases of execution that you are referring to can be represented using 3 states. There is a short video on the Stateflow webpage titled "Getting Started with Stateflow" that solves a similar problem.
The decision tree logic (if-else) in your design can either be written programmatically (using MATLAB language in the MATLAB function block) ,or drawn in a flow chart. Look in the Stateflow documentation for "What is a flow graph" and "Reusable functions in state charts". A more detailed (and slightly longer) video of how to use Stateflow for building such logic is available in "Control Logic Made Easy with Stateflow". You can then generate HDL code from this model using the MathWorks HDL coder product. Find more information about that on the HDL Coder product.
