Help wanted, C to state machines, or any alternatives.

You probably should begin by gaining a basic understanding of what HDL design is all about, either VHDL or System Verilog. The fundamental design space between C and HDL is different. C distributes an algorithm in time using memory. HDL distributes an algorithm in time and space using all available FPGA resources, which can be completely parallel, serial, or a combination of both in terms of the algorithm. With that said, having done what you are trying to do, I would suggest separate processes for generating the error signal, then another process for determination of whether you need to switch the phase leg high or low. The sequential control of the data from these processes could be done with simply hardware handshaking or more elegantly a finite state machine.