Help!!!!! SDRAM interface Cyclone III.

Tthanks a lot! I did it!

I added Ram onchip and check ok with "Hello world small". but the major problem is i can't still write or read into ddr2 sdram. i wonder i maped pins right?

module lab06 (

clkin_50,clkin_125, cpu_resetn,

ddr2bot_wen, ddr2bot_rasn, ddr2bot_casn,

ddr2bot_cke, ddr2bot_csn, ddr2bot_odt,

ddr2bot_a, ddr2bot_ba, ddr2bot_active,

ddr2top_wen, ddr2top_rasn, ddr2top_casn,

ddr2top_cke, ddr2top_csn, ddr2top_odt,

ddr2top_a, ddr2top_ba, ddr2top_active,

ddr2_dq, ddr2_dqs, ddr2_dm, ddr2_ck_p,

ddr2_ck_n);

output ddr2bot_active;

output ddr2top_active;

output [ 12: 0] ddr2bot_a;

output [ 1: 0] ddr2bot_ba;

output ddr2bot_casn;

output ddr2bot_cke;

output ddr2bot_csn;

output ddr2bot_odt;

output ddr2bot_rasn;

output ddr2bot_wen;

output [ 12: 0] ddr2top_a;

output [ 1: 0] ddr2top_ba;

output ddr2top_casn;

output ddr2top_cke;

output ddr2top_csn;

output ddr2top_odt;

output ddr2top_rasn;

output ddr2top_wen;

output [ 7: 0] ddr2_dm;

inout [ 63: 0] ddr2_dq;

inout [ 7: 0] ddr2_dqs;

inout [ 2: 0] ddr2_ck_n;

inout [ 2: 0] ddr2_ck_p;

input clkin_50;

input clkin_125;

input cpu_resetn;

nios_sys DUT (

// 1) global signals:

.clk_125 (clkin_125),

.clk_50 (clkin_50),

.ddr2_bot_aux_full_rate_clk_out (),

.ddr2_bot_aux_half_rate_clk_out (),

.ddr2_bot_phy_clk_out (),

.ddr2_top_aux_full_rate_clk_out (),

.ddr2_top_aux_half_rate_clk_out (),

.ddr2_top_phy_clk_out (),

.reset_n (cpu_resetn),

.sys_clk0 (),

// the_LED_pio

.out_port_from_the_LED ({ddr2top_active,ddr2bot_active}),

// the_ddr_bot

.global_reset_n_to_the_ddr2_bot (cpu_resetn),

.local_init_done_from_the_ddr2_bot (),

.local_refresh_ack_from_the_ddr2_bot (),

.local_wdata_req_from_the_ddr2_bot (),

.mem_addr_from_the_ddr2_bot (ddr2bot_a),

.mem_ba_from_the_ddr2_bot (ddr2bot_ba),

.mem_cas_n_from_the_ddr2_bot (ddr2bot_casn),

.mem_cke_from_the_ddr2_bot (ddr2bot_cke),

.mem_clk_n_to_and_from_the_ddr2_bot (ddr2_ck_n[0]),

.mem_clk_to_and_from_the_ddr2_bot (ddr2_ck_p[0]),

.mem_cs_n_from_the_ddr2_bot (ddr2bot_csn),

.mem_dm_from_the_ddr2_bot (ddr2_dm [7:4]),

.mem_dq_to_and_from_the_ddr2_bot (ddr2_dq [63:32]),

.mem_dqs_to_and_from_the_ddr2_bot (ddr2_dqs [7:4]),

.mem_odt_from_the_ddr2_bot (ddr2bot_odt),

.mem_ras_n_from_the_ddr2_bot (ddr2bot_rasn),

.mem_we_n_from_the_ddr2_bot (ddr2bot_wen),

.reset_phy_clk_n_from_the_ddr2_bot (),

// the_ddr_top

.global_reset_n_to_the_ddr2_top (cpu_resetn),

.local_init_done_from_the_ddr2_top (),

.local_refresh_ack_from_the_ddr2_top (),

.local_wdata_req_from_the_ddr2_top (),

.mem_addr_from_the_ddr2_top (ddr2top_a),

.mem_ba_from_the_ddr2_top (ddr2top_ba),

.mem_cas_n_from_the_ddr2_top (ddr2top_casn),

.mem_cke_from_the_ddr2_top (ddr2top_cke),

.mem_clk_n_to_and_from_the_ddr2_top (ddr2_ck_n[1]),

.mem_clk_to_and_from_the_ddr2_top (ddr2_ck_p[1]),

.mem_cs_n_from_the_ddr2_top (ddr2top_csn),

.mem_dm_from_the_ddr2_top (ddr2_dm [3:0]),

.mem_dq_to_and_from_the_ddr2_top (ddr2_dq [31:0]),

.mem_dqs_to_and_from_the_ddr2_top (ddr2_dqs [3:0]),

.mem_odt_from_the_ddr2_top (ddr2top_odt),

.mem_ras_n_from_the_ddr2_top (ddr2top_rasn),

.mem_we_n_from_the_ddr2_top (ddr2top_wen),

.reset_phy_clk_n_from_the_ddr2_top (),

// the_pll

.locked_from_the_pll (),

.phasedone_from_the_pll()

)

;

endmodule