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Altera_Forum's avatar
Altera_Forum
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17 years ago

Help RAM

hi, i am quite new to vhdl and quartus ii. i have coded a 16x8 ram using vhdl in quartus , and y need a ram of 256kb , when y chage the address_width to 131072, that is the number of bits that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Didn't see DATA_WIDTH set to 16. My calculation was for the case where DATA_WIDTH set to 8, my bad.

Princess, the ram design inference that Rysc was referring to will be noted in the info or warning (I can't remember which one exactly) output during synthesis. Looking at the code, it looks like it should infer it, but maybe not.

I was going to suggest the following, but sync FvM already tried the design and it worked for him it probably won't have much fruit:

Also, it is going to generate a 2-port RAM since the address lines for read and write are different.

If you see nothing about ram inferrence in the synthesis log, you might want to try and see if it will synthesize as a 1-port module (use same address line for read/write), then if it works, it would appear as though quartus is having an issue with the 2-port implementation.