Help RAM

Question

hi,  i am quite new to vhdl and quartus ii. i have coded a 16x8 ram using vhdl in quartus , and y need a ram of 256kb , when y chage the address_width  to 131072, that is the number of bits that y need, so when i try to compile  appears  this  warning (10639): vhdl warning at test.vhd(23): constant value overflow warning (10445): vhdl subtype or type declaration warning at test.vhd(23): subtype or type has null range warning (10034): output port "q[15]" at test.vhd(18) has no driver warning (10034): output port "q[14]" at test.vhd(18) has no driver . . . warning (10034): output port "q[0]" at test.vhd(18) has no driver  so ... how i make a ram of 256kb?

altera_forum · Answer

256Kx8 is pretty large for inside an FPGA, but probably doable in some parts.  The warnings have nothing to do with the size of RAM, but the VHDL, which nobody has.  Double-click on the first message, and usually takes you to a location in the code(when possible) and start debugging that.  The other messages may be an off-shoot from that initial error.

altera_forum · Answer

but... what is the correct way to do it?

this is my code ... but something is wrong in it ... help me

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY Test IS

GENERIC

(

ADDRESS_WIDTH : integer := 131072;

DATA_WIDTH : integer := 16

);

PORT

(

clock : IN std_logic;

data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);

write_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);

read_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);

we : IN std_logic;

q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)

);

END Test;

ARCHITECTURE rtl OF Test IS

TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);

SIGNAL ram_block : RAM;

BEGIN

PROCESS (clock)

BEGIN

IF (clock'event AND clock = '1') THEN

IF (we = '1') THEN

ram_block(to_integer(unsigned(write_address))) <= data;

END IF;

q <= ram_block(to_integer(unsigned(read_address)));

END IF;

END PROCESS;

END rtl;

altera_forum · Answer

Hi Princess,

If you want 256 KB (assuming kilo-byte) of ram, that is 256 * 1024 = 262144 bytes

To store that many bytes, assuming that your memory is byte-addressable (location 1234 referts to 8 bits, location 1235 refers to the next 8 bits), you need to find the next greatest (or equal) power of 2. So:

2^0 = 1

2^1 = 2

2^2 = 4

2^3 = 8

...

2^18 = 262144

So, ADDRESS_WIDTH is 18, not 131072. The ADDRESS_WIDTH parameter refers to how many wires represent your address (or, how many bits).

What's probably happening is that your synthesis/simulator tool can't handle a bus width of 131072 for a vector - this is incredibly large.

The other warnings are probably due to the same issue, as your synthesis/simulator tool appears to have assumed that the width of RAM is 0.

altera_forum · Answer

thanks, i understood it, but ... i think address_width have to be in bits, not in bytes ... so it would be 2 ^ 21 and put 21 in the address_width, andi get the following errors... please correct me if i'm wrong.  Error: Out of memory in module quartus_map.exe (2141 megabytes used) Error: Current module quartus_map ended unexpectedly

altera_forum · Answer

The calculation is clearly wrong. A 256 kByte RAM with a data with of 16 has 128 k words. This is equivalent to only 2^17 addresses, in other words an address width of 17

The reported Quartus out of memory error may result from trying to synthetisize an unavailable large RAM.

It may be meaningful to check first, if your present FPGA device has sufficient internal RAM. You would need at least an EP3C55 or larger Stratix device.

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