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Altera_Forum
Honored Contributor
17 years agoHelp RAM
hi, i am quite new to vhdl and quartus ii. i have coded a 16x8 ram using vhdl in quartus , and y need a ram of 256kb , when y chage the address_width to 131072, that is the number of bits that...
Altera_Forum
Honored Contributor
17 years agoHi Princess,
If you want 256 KB (assuming kilo-byte) of ram, that is 256 * 1024 = 262144 bytes To store that many bytes, assuming that your memory is byte-addressable (location 1234 referts to 8 bits, location 1235 refers to the next 8 bits), you need to find the next greatest (or equal) power of 2. So: 2^0 = 1 2^1 = 2 2^2 = 4 2^3 = 8 ... 2^18 = 262144 So, ADDRESS_WIDTH is 18, not 131072. The ADDRESS_WIDTH parameter refers to how many wires represent your address (or, how many bits). What's probably happening is that your synthesis/simulator tool can't handle a bus width of 131072 for a vector - this is incredibly large. The other warnings are probably due to the same issue, as your synthesis/simulator tool appears to have assumed that the width of RAM is 0.