help please......frequency divider

if im using std_logic_vector type...how?

generic(n: natural :=25);

port( divCLK: in std_logic;

level:in std_logic_vector (3 downto 0);

Q: out std_logic);

end countersystem;

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architecture behv of countersystem is

signal clkdiv: std_logic_vector(n-1 downto 0);

begin

process(divCLK)

begin

if rising_edge(divCLK) then

clkdiv <= clkdiv + 1;

end if;

Q<=clkdiv(24);

from this i can get 1Hz, but how to get 2Hz,3Hz and so on from these coding...

is it

Q<=clkdiv(23),Q<=clkdiv(22)...and so on?

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how to convert 25Mhz to 1hz,2hz till 10 hz....?

and use level select to select the frequency..this is the detail:

level 1-10 will select to frequency 1Hz to 10Hz..

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A counter that counts down from either 12,500,000 (1 Hz); 6,250,000 (2 Hz)...1,250,000 (10 Hz) would be a place to start. When the counter counts down and rolls over from 0 back to the max listed above, then toggle the output clock.

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i just can do till 1 Hz only but still dont know whether its correct or not....:(

tq....

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Use a simulator and measure the output clock period.

Kevin Jennings