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Altera_Forum
Honored Contributor
14 years agoif im using std_logic_vector type...how?
generic(n: natural :=25); port( divCLK: in std_logic; level:in std_logic_vector (3 downto 0); Q: out std_logic); end countersystem; ---------------------------------------------------- architecture behv of countersystem is signal clkdiv: std_logic_vector(n-1 downto 0); begin process(divCLK) begin if rising_edge(divCLK) then clkdiv <= clkdiv + 1; end if; Q<=clkdiv(24); from this i can get 1Hz, but how to get 2Hz,3Hz and so on from these coding... is it Q<=clkdiv(23),Q<=clkdiv(22)...and so on?