Honored ContributorMy source clock could range from 25MHz to 165MHz depending on the video format. Is there a way to ensure the PLL will lock onto it. I also need the output clock to be 90 degree shifted.
I don't think ATLPLL_RECONFIG will do what this. Any suggestion will be much appreciated.
Honored ContributorBTW, I'm using Cyclone IV E.
Honored ContributorI think, PLL reconfiguration would be the correct way to achieve the synchronisation to a wide input frequency range. Obviously you have to implement a rough frequency measurement to select the range.
Although the PLL MegaFunction setup is using an exact frequency specification, a PLL can basically lock over the 600-1300 MHz VCO frequency range for a fixed divider ratio, so 3 ranges would cover the said application. The loop filter settings are however representing a trade-off between different requirements and possibly not optimized for a wide lock range. You'll find some articles in the Altera knowledgebase discussing lock range optimization: http://www.altera.com/support/kdb/solutions/rd01152007_962.html The actual lock range for a particular PLL setup is shown in the fitter report. I ususally see a 1:2 lock range with Cyclone III projects, I guess it's similar with Cyclone IV.Honored ContributorI have looked at the PLL lock range in the Fitter report and you're right, I see almost 1:2 lock range. Because in my design, the input ranges from 25MHz to 165MHz, that's why I need some help from your guys.
I will check the link you provided, and thank you for your comment/suggestion.Honored ContributorI read that solution yesterday. What that method do is it helps you extract valid parameter values for the PLL. You can put in Fmin for clko and Fmax for clk1, it tells you if your input goes beyond the lock range that the PLL is capable of, so it is not what I'm looking for.
Honored ContributorHonored ContributorI know and I guess I will have to come up with something to work around this. Thanks for your comment.
