help on PLL input frequency

I think, PLL reconfiguration would be the correct way to achieve the synchronisation to a wide input frequency range. Obviously you have to implement a rough frequency measurement to select the range.

Although the PLL MegaFunction setup is using an exact frequency specification, a PLL can basically lock over the 600-1300 MHz VCO frequency range for a fixed divider ratio, so 3 ranges would cover the said application. The loop filter settings are however representing a trade-off between different requirements and possibly not optimized for a wide lock range. You'll find some articles in the Altera knowledgebase discussing lock range optimization: http://www.altera.com/support/kdb/solutions/rd01152007_962.html

The actual lock range for a particular PLL setup is shown in the fitter report. I ususally see a 1:2 lock range with Cyclone III projects, I guess it's similar with Cyclone IV.