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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help needed for this 3 bit parity generator/checker.

:cry: Im a total Noob and seriously need help in my VHDL.

the question:

To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_out and even_out). When the number of high level input is odd, odd_out is kept HIGH and even_out output LOW. Likewise, if the number of high level input is even, even_out is kept HIGH and odd_out LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    A BIG THANK YOU TO LETS AND TRICKY. Today i used ur advices and finally got the vhdl runnning. Using the XOR operations and IF-ELSE. thanks guys. :D

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    please can i have a clear format for a 9 bit parity generator/checker.. if to use a loop how will it look like...

    please

    many thanks