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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help needed for this 3 bit parity generator/checker.

:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_Forum's avatar
Altera_Forum
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12 years ago

please can i have a clear format for a 9 bit parity generator/checker.. if to use a loop how will it look like...

please

many thanks