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Altera_Forum
Honored Contributor
15 years agoHelp needed for this 3 bit parity generator/checker.
:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_Forum
Honored Contributor
15 years agoA BIG THANK YOU TO LETS AND TRICKY. Today i used ur advices and finally got the vhdl runnning. Using the XOR operations and IF-ELSE. thanks guys. :D