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6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It's clearly wrong to place a pull-up resistor at TCK, a pull-down resistor is needed instead.

    P.S.: Also the CLK AC coupling seems faulty, but it hopefully wouldn't block JTAG communication.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    It's clearly wrong to place a pull-up resistor at TCK, a pull-down resistor is needed instead.

    P.S.: Also the CLK AC coupling seems faulty, but it hopefully wouldn't block JTAG communication.

    --- Quote End ---

    Thanks Mr FvM! I'll check the circuit board and try it again. If you have another idea, hooefully we can discuss. Thanks very much.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    But you can spell out why TCK node is wrong??? I think TCK is the same as the others

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Altera's guidelines recommend TCK be tied to GND through a 1K resistor.

    I don't have Altium Designer and haven't looked at your schematic. However, I've found that many JTAG signal integrity problems can be solved by adding source-series termination to the JTAG signals. So for example, a 33ohm or 50ohm resistor on TCK, TDI, and TMS right at your JTAG connector. Also, a resistor on TDO coming out of the FPGA.

    I'm not saying this is your issue. Usually if signal integrity is a problem, you'll at least be able to scan the chain even if only intermittently.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Altera's guidelines recommend TCK be tied to GND through a 1K resistor.

    I don't have Altium Designer and haven't looked at your schematic. However, I've found that many JTAG signal integrity problems can be solved by adding source-series termination to the JTAG signals. So for example, a 33ohm or 50ohm resistor on TCK, TDI, and TMS right at your JTAG connector. Also, a resistor on TDO coming out of the FPGA.

    I'm not saying this is your issue. Usually if signal integrity is a problem, you'll at least be able u to scan the chain even if only intermittent.

    Jake

    --- Quote End ---

    ! Yo

    Thanks Mr jacobjone! you know, my design have a problem for long time, it made me trouble so I 'll check your advice. But you can tel me how to scan the chain.....