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Altera's guidelines recommend TCK be tied to GND through a 1K resistor.
I don't have Altium Designer and haven't looked at your schematic. However, I've found that many JTAG signal integrity problems can be solved by adding source-series termination to the JTAG signals. So for example, a 33ohm or 50ohm resistor on TCK, TDI, and TMS right at your JTAG connector. Also, a resistor on TDO coming out of the FPGA.
I'm not saying this is your issue. Usually if signal integrity is a problem, you'll at least be able u to scan the chain even if only intermittent.
Jake
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! Yo
Thanks Mr jacobjone! you know, my design have a problem for long time, it made me trouble so I 'll check your advice. But you can tel me how to scan the chain.....
Honored Contributor
