help me to translate verilog to vhdl

hello,

is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl..

`timescale 1ns / 1ps

module mctrl(

input clk,

input rst,

output [31:0] wb_o_dat,

output wb_o_ack,

input [31:0] wb_i_adr,

input [3:0] wb_i_sel,

input wb_i_we,

input [31:0] wb_i_dat,

input wb_i_cyc,

input wb_i_stb,

output wb_o_err,

inout [31:0] GPIO,

input [31:0] GPIO_I

);

wire sel_ram;

wire sel_rom;

wire sel_io;

wire sel_ddr;

localparam RAM_BITS=11;

localparam ROM_BITS=14;

localparam IO_BITS=16;

wire [RAM_BITS-1:0] ram_addr;

wire [ROM_BITS-1:0] rom_addr;

wire [IO_BITS-1:0] io_addr;

wire [31:0] ramdata;

wire [31:0] romdata;

wire [31:0] iodata;

wire ram_ack_o;

wire rom_ack_o;

wire io_ack_o;

wire rom_err;

wire io_err;

wb_bram# ( .ASIZE(RAM_BITS) ) my_ram (

.clk ( clk ),

.rst ( rst ),

.ce ( sel_ram ),

.we ( wb_i_we ),

.addr( ram_addr ),

.dati( wb_i_dat ),

.dato( ramdata ),

.ack ( ram_ack_o )

);

wb_prom my_rom (

.clk ( clk ),

.rst ( rst ),

.we ( wb_i_we ),

.ce ( sel_rom ),

.addr( rom_addr ),

.dato( romdata ),

.dati ( wb_i_dat ),

.ack ( rom_ack_o )

);

wb_io my_io (

.clk ( clk ),

.rst ( rst ),

.ce ( sel_io ),

.we ( wb_i_we ),

.addr ( io_addr ),

.dato ( iodata ),

.dati ( wb_i_dat ),

.ack (io_ack_o),

.err ( io_err ),

.mask ( wb_i_sel ),

.GPIO ( GPIO ),

.GPIO_I ( GPIO_I )

);

reg ack_int;

assign ram_addr = wb_i_adr[RAM_BITS-1:0];

assign rom_addr = wb_i_adr[ROM_BITS-1:0];

assign io_addr = wb_i_adr[IO_BITS-1:0];

wire op;

assign op = wb_i_cyc && wb_i_stb;

assign sel_ram = op && (wb_i_adr[31:30] == 2'b11);

assign sel_rom = op && (wb_i_adr[31:30] == 2'b00);

assign sel_io = op && (wb_i_adr[31:30] == 2'b01);

assign wb_o_dat =

sel_ram ? ramdata :

sel_rom ? romdata :

iodata;

assign wb_o_ack = ram_ack_o | rom_ack_o | io_ack_o;

assign wb_err_o = 0;

// synthesis translate_off

always @(posedge clk)

begin

if (wb_i_we && sel_rom && wb_i_adr[31:5] != 0) begin

$display("%t: Invalid write to ROM: Address %h\n", $time, wb_i_adr[12:0]);

$stop;

end

end

// synthesis translate_on

endmodule