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Altera_Forum's avatar
Altera_Forum
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17 years ago

help me to translate verilog to vhdl

hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Why do you want to translate this code into VHDL? You may use it in Quartus II together with VHDL modules with no translation required. I have used mixed VHDL-Verilog implementation sometimes, and everything works well in Quartus.