Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorhelp me to translate verilog to vhdl
hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_ForumHonored Contributor
Honored ContributorWhy do you want to translate this code into VHDL? You may use it in Quartus II together with VHDL modules with no translation required. I have used mixed VHDL-Verilog implementation sometimes, and everything works well in Quartus.
