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Altera_Forum
Honored Contributor
Honored Contributorhelp me to translate verilog to vhdl
hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_ForumHonored Contributor
Honored Contributorbecause this code is written by other people and i do understand very little from verilog. thats why i want to convert it into vhdl because i can understand..
