Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

help me to translate verilog to vhdl

hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Why do you want to translate this code into VHDL? You may use it in Quartus II together with VHDL modules with no translation required. I have used mixed VHDL-Verilog implementation sometimes, and everything works well in Quartus.

--- Quote End ---

How is it possible please ? I tried to do that, and when compiling, I have VHDL error syntax..

Ps: My file name is My_example_top.vhd should I change it to .v ?