Altera_ForumHonored Contributor17 years agohelp me to translate verilog to vhdl hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...Show More
Altera_ForumHonored Contributor17 years agoyes...it's also verilog..did u mean that it can't be converted???
Recent DiscussionsAgilex 7 (F-tile/R-tile) PCIe Gen5 RX Compliance Test Issue -some lanes can't enter LoopbackLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMA