help in for loop

Question

sir,here is my small code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity nu is

Port ( ---a : in STD_LOGIC_VECTOR (6 downto 0);

b : out STD_LOGIC_VECTOR (6 downto 0));

end nu;

architecture Behavioral of nu is

constant f : std_logic_vector(7 downto 0) :="01011001";

signal result : integer;

begin

k1 : for i in 0 to 4 generate

result <= conv_integer(signed(f))*i;

b <= conv_std_logic_vector(result,7);<--- error in this line.

end generate;

end Behavioral;

Analyzing Entity <nu> in library <work> (Architecture <Behavioral>).

ERROR:Xst:800 - "C:/.Xilinx/gateor/float.vhd" line 44: Multi-source on Integers in Concurrent Assignment.

plz fix my problem.

altera_forum · Answer

you have assigned to b 5 times.  secondly this is an altera forum, you are using xilinx tools

altera_forum · Answer

--- Quote Start ---

k1 : for i in 0 to 4 generate

result <= conv_integer(signed(f))*i;

b <= conv_std_logic_vector(result,7);<--- error in this line.

end generate;

--- Quote End ---

A common misunderstanding of HDL loops:

Your loop is unrolled at compile time to:

result <= conv_integer(signed(f))*0;