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Altera_Forum's avatar
Altera_Forum
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18 years ago

HELP: How to Use sopc to W/R two FLASH ?

In my work, I plan to use two flash to store the data sheet, which are two seperate data sheet. In the same clock cycle, FPGA can get the two flash data. Actually speaking, the data sheet are all 16bit data-width , so with two 16bit data-width flash , I can get 32 bit data-width at the same time.

When I add "cfi_flash_0" and "cfi_flash_1" into SOPC ,both of them link to "tristate_master" , can I control the two flash seperately when I write them and read them at the same time ? they all link to "tristate_master" !

Hope for your reply!

Thanks very much!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The Nios CPU works according to my programm , can I control the two flash at the same time? I mean using the same data addres to read the both flash , so I can get 32 bits data-width at the same clock cycle. If it can't work , do I have to make the two flash data addres seperately?

    Could you explain more about it, mirimon?

    Thanks very much!
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    so, NIOS support 32 bit of FLASH, you just using all of the same signal at the FLASH, excpte data port.

    eg. FLASH_1 for data[15..0], FLASH_2 for data[31..16]
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    --- Quote Start ---

    The Nios CPU works according to my programm , can I control the two flash at the same time? I mean using the same data addres to read the both flash , so I can get 32 bits data-width at the same clock cycle. If it can't work , do I have to make the two flash data addres seperately?

    Could you explain more about it, mirimon?

    Thanks very much!

    --- Quote End ---

    If you put two FLASH device on the same TriState bridge, you will get common Add, Data, R/w, ByteEnale signals and dedicated CS signals. From the CPU side, acceding to FLASH_0 is writin at FLASH_0 address and same for Flash_1. If you want CPU to access the two device at the same time, you will have to add extra logic at the top of your design to drive the two CS. Then, using ByteEnable, you can drive 8, 16 or 32bits and by using external logique, you will access lsb or msb flash.

    The second and straight forward approach is to declare only one FLASH (32bits if FLASH_0 and FLASH_1 are 16bits, 16bits if 8bits) and be aligned on the worst case timing. Then, you will get only one CS and the SOPC_BUILDER will manage directly for you the byteenable to address the proper FLASH

    Maga
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Aha. It is in this wise.Thank you very much, Maga.

    I use Quartus 5.1 and find there is no "Program a file into flash memory" choice menus in Flash Programmer with Nios2 . It means that I have no way to write my " .bin" to flash , what about other edition of Quartus?

    If I go on work with 5.1 edition , I can write my data sheet with MCU(Single Chip Micyoco）。I think there are two ways to read the data in the flash , one is to read them with a driver designed with VHDL or verilog, the other one is to use Nios2. Does anyone have the related experience ? I mean using the two ways to read the data from flash.

    Could someone attch some metierials or programs?

    Thanks very much.

    --Yang