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The Nios CPU works according to my programm , can I control the two flash at the same time? I mean using the same data addres to read the both flash , so I can get 32 bits data-width at the same clock cycle. If it can't work , do I have to make the two flash data addres seperately?
Could you explain more about it, mirimon?
Thanks very much!
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If you put two FLASH device on the same TriState bridge, you will get common Add, Data, R/w, ByteEnale signals and dedicated CS signals. From the CPU side, acceding to FLASH_0 is writin at FLASH_0 address and same for Flash_1. If you want CPU to access the two device at the same time, you will have to add extra logic at the top of your design to drive the two CS. Then, using ByteEnable, you can drive 8, 16 or 32bits and by using external logique, you will access lsb or msb flash.
The second and straight forward approach is to declare only one FLASH (32bits if FLASH_0 and FLASH_1 are 16bits, 16bits if 8bits) and be aligned on the worst case timing. Then, you will get only one CS and the SOPC_BUILDER will manage directly for you the byteenable to address the proper FLASH
Maga
Honored Contributor
