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Altera_Forum
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18 years ago

help about cycloneII!!!!

hi all

I'm using the cycloneII(EP2C20Q240C8).I want to know how to use the pin of PLL_OUTn

IN the pin sheet,pin description of PLL_OUTn is:Optional negative terminal for external clock outputs from PLL[1..4],These pins can only use the differential I/O standard if it is being fed by a PLL output.

What is it mean? I assign the sdd3 of sdram to PLL_OUTn and it doesn't work.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi dd412,

    in Cyclone and Cyclone II devices the PLL_OUTn pins can not be used as single ended clock output. Ths means that you cann only use PLL_OUTp pins to route PLL signals out to the PCB when using single ended output standards like lvcmos or lvttl.

    The other thing is, that you can use the PLL_OUTn and PLL_OUTp pins only as clock LVDS-Pair when using LVDS standard, not as LVDS-User I/O.

    When using single ended I/O standards you can use the PLL_OUTn pins as user I/O

    Christian
  • Altera_Forum's avatar
    Altera_Forum
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    If you are not using a differential standard for the output clock PLL_OUT then the PLL_OUTn will be unused and can be used as a regular I/O or no connect if not needed in your design.

  • Altera_Forum's avatar
    Altera_Forum
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    thank you for your help!

    I use PLL1_OUTp as single ended clock output(sdram_clk) and PLL1_OUTn as sdd3 of sdram in my design.It doesn't work.If I use PLL3_OUTp as sdram_clk and unuse PLL1_OUTp ,sucessful!!!!

    But why?
  • Altera_Forum's avatar
    Altera_Forum
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    Do you get an error message when compiling or does it fail on the board? I'm trying to figure out what you mean by it doesn't work.

  • Altera_Forum's avatar
    Altera_Forum
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    Also please specify which I/O standards are assigned to each output clock.

  • Altera_Forum's avatar
    Altera_Forum
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    The sdram is 48LC4M16A2-75 in my project.It work well when I use the PLL3_OUTp as the sdram_clk and PLL1_OUTn as sdd3.There is no error when I complie my project.I/O standard is LVTTL.

  • Altera_Forum's avatar
    Altera_Forum
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    The PLL_OUTn pins can either be the negative pin for a differential pair if the clock output is using a differential I/O standard. If not then it can only be used as a regular I/O pin. This pin still needs to follow all of the other pin placement rules due to current strength and switching noise. Check to see if you are following the pin placement guidelines in the handbook for I/O pins. Also when it "isn't working", check to see if you are getting any error messages for a clue on why it isn't compiling. It could be an I/O placement rule was violated.