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Altera_Forum
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16 years ago

Help - nStatus won't release, EP3C5 custom board

I'm having trouble programming a Cyclone III on our custom board via JTAG. The nstatus pin won't release yet I can't find anything wrong with the voltages on the board. Could something else keep device in reset?

Here are images of the relevant parts of the schematic: http://hygren.nu/osc-board/

Does anyone have any ideas?

EDIT:

Forgot to mention, the short-circuit on the power image (http://hygren.nu/osc-board/power0.png) pins 35,36 and 107,108 has been fixed.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ok, will look into that on our respin of this board. Thanks again!

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You need extra protection against overshoot when using 3.3V I/O on cyclone III, because they don't tolerate more than 4.1V. This is especially true for the JTAG interface as those pins don't have clamping diodes in the FPGA, and the JTAG cable connection is likely to cause an impedance mismatch that will create overshoot.

    To avoid problems, Altera recommends to use 2.5V for the JTAG power, or to put extra clamping diodes if you stay on 3.3V (actually they recommend the extra diodes when adding a connector to configure the EPCS chip, but this recommendation can also be used for the JTAG pins).
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    By the way, what you do mean by an unprotected JTAG interface?

    --- Quote Start ---

    I don't see anything wrong, except that you use 3.3V without protection for the JTAG interface, which isn't recommended and could destroy the FPGA.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Alright, well, it's very strange, but it works : )

    Thanks a lot for your help Daixiwen!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The state of a pin during reconfiguration is tristate with weak pull-up (more than 7kOhm under 3.3V).

    I don't know why you would have a difference between the two programming files, it is really strange.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Switched to my other programming file (.jbc) generated at the same time as my normal one (.sof), now it works (!!!), how is that possible?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for your reply, simultaneously I burrowed through other similar threads and found that many had issues with the bottom slug not being connected. I was unsure of this on our board and fortunately had a hole right under the FPGA that was grounded so I put _a lot_ of soldering paste there.

    Now the JTAG works but CONFIG_DONE won't come high afterwards, what does that usually indicate? The CONFIG_DONE is, as you can see in the schematics, pulled high by a 10kOhm resistor, but it is also connected to a normal I/O on bank 8 and another 10kOhm pull-up. What are the characteristics of an I/O when the device is not configured?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I don't see anything wrong, except that you use 3.3V without protection for the JTAG interface, which isn't recommended and could destroy the FPGA.

    Did you check the quality of the JTAG signals with an oscilloscope?