Hello everyone, I need your help I'm using ADC AD9254 and DAC 5672, with FPGA DE10 standard, I want to acquire data, so Implement this code: the data out is associated to The dac, I get the result below:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY Co IS

port (clk: in std_logic;

reset: in std_logic;

DCO: in std_logic;

Data_valid: out std_logic;

Data_in: in std_logic_vector(13 downto 0);

Data_out: out std_logic_vector (13 downto 0)

);

end;

architecture Co_arch of Co is

signal count : std_logic_vector(13 downto 0);

begin

process(clk,reset)

begin

if reset='1' then

count<= (others=>'Z');

elsif rising_edge(Clk) then

if DCO='1' then

count<=Data_in;

Data_valid<='1';

else

count<= (others=>'Z');

Data_valid<='0';

end if;

end if;

Data_out<= count;

end process;

end Co_arch;