HDL error when making digital clock

the first code suggest you're trying to detect two clock edges at exactly the same time - and you cannot do that (in any circuit). the second one just looks for some signals to be a specific level when the clock has a rising edge.

You will have to do an edge detector inside your clocked process. For example if you create a signal second_edge_delayed that is the value of second_edge on the previous cycle, then detecting a rising edge on second_edge becomes

if(second_edge_delayed='0' and second_edge='1') then