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Altera_Forum's avatar
Altera_Forum
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11 years ago

Has anyone successfully inferred read enable ports on true dual-port ram?

The megawizard successfully produces the following true dual-port altsyncram code with read enables: // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module ram_dp ( ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Ok - had another read. Instead of making the read enable and "else if " against the write enable, just make it a stand alone "if". You would never expect the read port to be controlled by the write_enable - they should not be mutually exclusive. 


always @ (posedge clk_a)
    begin
        // Port A 
        if (we_a) 
        begin
            ram <= data_a;
      end
        
      if (re_a)
        begin
            q_a <= ram;
        end 
    end