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Honored Contributor
Honored ContributorHas anybody ever write data to ssram on C3-starter-kit using vhdl?
I am using a 10M sram_clk to write data to the ssram on C3-starter-kit board. The inside clk has a 180 degree phrase compared to sram_clk. I wrote data in single cycle and read in three cycles....
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I haven't checked the datasheet, but shouldn't you keep ADSC low for one more cycle so that the SRAM gets your new read address? --- Quote End --- Thank you,Daixiwen Yes,i got right data when i keep ADSC low before read. The ADSP_n is pull up to high.I thought i could use single read model,but not.I got right at pipelined read model.
