Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hardening an IP

Hi,

I am in the need of hardening an IP, which can be used for final integration into the chip level netlist(vqm) and then generate the programming files(JIC).

Right now i am always reading the source files of the IP with the VQM of the final chip netlist, which is more time consuming.

I can do a VQM of the IP and use it with the chip level VQM, instead i was wondering if i could create a hard logic partition of the IP and re use it always.

Please share your ideas if there are better ways of implementing. Thanks in advance.

Regards,

Srinivas

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    You can create a partition for your IP and export it as a post-fit netlist. This way it will always be placed on the same LUTs every time, so as long as this is acceptable then you can try that.

    This can make fitting other parts harder as it gives them less scope to move around to fix their timing, but it means this IP should always meet timing.