Hard Memory controller vs Soft Memory Controller

The 28nm FPGAs all have dedicated logic for memory controllers, so even a "soft" implementation will use some special hardware. But ArriaV/CycloneV have a truly hard implementation too(it's not just a few IO structures like the DLL -> DQS strobe, but the whole controller is hardened). I'm sure the fit reports say something about it, but haven't looked. In the MegaWizard for these devices there is a checkbox on the front page that says whether it's hard or soft. The hardened one saves resources(since you won't use that logic for anything else) and it's very good as a multi-port memory controller. (Not that you can't create a multi-port with a soft controller, it's just more logic, naturally). The device handbook should talk about the hardened one.