Handshake problem

I'm not sure I understand what you mean.

If ck1 and ck2 are unrelated, i.e. without an exact phase relation, using them to directly clock the system could lead you to unexpected behaviour.

You'd better use a single clock. For example, if ck1/ck2 frequencies are not so high and if you can generate extra clocks with a pll, you can create a single clock with a period of 1 and use it instead of ck1 and ck2. This approach would require minor changes in your Timer and PulseGen modules, but it would lead to a more robust design.

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I tought mabe there is a solution i know nothing about, even i don't think this is possible.

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Nothing is impossible (ok, let's say almost nothing...).

There are a few ways to do what you need, but this depends on some unspecified details; for example:

- where ck1 and ck2 come from? (external? generated from fpga?)

- is there a fixed phase relation between them

- what can you change and what not

In the worst case where ck1 and ck2 run independently and you don't have a higher frequency clock, your signals would necessarily suffer a time uncertaintly up to the maximum among ck1 and ck2 period. This is unavoidable. You can reduce it to half by sampling on both edges, but I would not recommend this.

Hi,

try the following scheme (check attachment).

I would suggest to run sim first.

Secondly this scehme transfers only one pulse at a time, you may improve the circuit as per requirement, and finally,

everything is possible , provided we dont set unreasonable constraints.

In your case it looks possible.