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I tought mabe there is a solution i know nothing about, even i don't think this is possible.
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Nothing is impossible (ok, let's say almost nothing...).
There are a few ways to do what you need, but this depends on some unspecified details; for example:
- where ck1 and ck2 come from? (external? generated from fpga?)
- is there a fixed phase relation between them
- what can you change and what not
In the worst case where ck1 and ck2 run independently and you don't have a higher frequency clock, your signals would necessarily suffer a time uncertaintly up to the maximum among ck1 and ck2 period. This is unavoidable. You can reduce it to half by sampling on both edges, but I would not recommend this.
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