Altera_ForumHonored Contributor7 years agoHandling generic parameters in Quartus II 16.1 VHDL Hello to everyone, I fpga and vhdl begginer and I am currently working on university project which concerns some array calculations on Cyclone V fpga and VHDL and I have a problem. All cust...Show More
Altera_ForumHonored Contributor7 years agothe problem is you didnt constrain the 2nd dimension - the std_logic_vector
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