Handling generic parameters in Quartus II 16.1 VHDL

In couple of following lines are given component declarations and "problematic" signal that port maps these components:

* this is custom type from package:

type Vector_aray is array(natural range <>) of std_logic_vector;

* this is first component:

component Main is

generic

(

BITS : integer;

CORE : integer

);

port

(

clock : in std_logic;

in_data : in Vector_aray(CORE-1 downto 0);

avg : in integer;

out_data : out std_logic_vector ((BITS-1) downto 0)

);

end component Main;

* this is second component:

component BLOCKS is

generic

(

BITS : integer;

CORE : integer

);

port

(

clock : in std_logic;

reset : in std_logic;

data_in : in std_logic_vector ((BITS-1) downto 0);

dout_line : out Vector_aray(CORE-1 downto 0)

);

end component BLOCKS;

* this is signal that connects stated arrays:

signal sLine : Vector_aray(CORE-1 downto 0);