Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Handling generic parameters in Quartus II 16.1 VHDL

Hello to everyone,

I fpga and vhdl begginer and I am currently working on university project which concerns some array calculations on Cyclone V fpga and VHDL and I have a problem.

All custom made types are defined in package and also array dimensions are defined there too and this package is included in all .vhd files because these custom types are used as ports for some entities.

The problem starts when I try to extract array dimensions out of package, as generic for top-level entity.

I have found here some previous posts that I have modified into this:

type myArray is array(natural range <>) of std_logic_vector;

but this still does not work and later during instantiation of an component, quartus reports an error that unconstrained arrays are not allowed so it won't connect all necessary components.

Can anyone help me to achieve all things related to generic parameters and how to avoid this problem?

Regards,

Al

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Set the VHDL mode to 2008. Unconstrained array types (where the element type is unconstrained) are only supported from 2008.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Thanks for the help but code still cannot be compiled. I managed to avoid one constraint but I think that the other makes problem now, the one that concerns size of a std_logic_vector.

    Idea was to have a variable length of an array and variable size of an vector, so is there any chance to solve this too?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    can you post the code? Unconstrained types are allowed, but signals must be constrained when they are declared.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    In couple of following lines are given component declarations and "problematic" signal that port maps these components:

    * this is custom type from package:

    type Vector_aray is array(natural range <>) of std_logic_vector;

    * this is first component:

    component Main is

    generic

    (

    BITS : integer;

    CORE : integer

    );

    port

    (

    clock : in std_logic;

    in_data : in Vector_aray(CORE-1 downto 0);

    avg : in integer;

    out_data : out std_logic_vector ((BITS-1) downto 0)

    );

    end component Main;

    * this is second component:

    component BLOCKS is

    generic

    (

    BITS : integer;

    CORE : integer

    );

    port

    (

    clock : in std_logic;

    reset : in std_logic;

    data_in : in std_logic_vector ((BITS-1) downto 0);

    dout_line : out Vector_aray(CORE-1 downto 0)

    );

    end component BLOCKS;

    * this is signal that connects stated arrays:

    signal sLine : Vector_aray(CORE-1 downto 0);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    the problem is you didnt constrain the 2nd dimension - the std_logic_vector