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Altera_Forum
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8 years ago

Handling generic parameters in Quartus II 16.1 VHDL

Hello to everyone, I fpga and vhdl begginer and I am currently working on university project which concerns some array calculations on Cyclone V fpga and VHDL and I have a problem. All cust...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thanks for the help but code still cannot be compiled. I managed to avoid one constraint but I think that the other makes problem now, the one that concerns size of a std_logic_vector.

Idea was to have a variable length of an array and variable size of an vector, so is there any chance to solve this too?