Handle DMA Page address received at the FPGA end during DMA transfer

Scatter Gather DMA transfer of 461KB is initiated from the Host PC to the ARRIA2GX FPGA using Jungo Driver.

During the transfer apart from the actual data sent as input data , extra data which looks like set of Page address( Physical address ) which keeps varying all the time

for ex :

0X0000000000020400(64bit) & 0X1cb2b00000000000(64bit)

0X0000000000020800(64bit) & 0X2b42600000000000(64bit)

0X0000000000020800(64bit) & 0X165df00000000000(64bit)

0X0000000000021400(64bit) & 0X2ccf500000000000(64bit)

0X0000000000022800(64bit) & 0X165df00000000000(64bit)

0X0000000000021800(64bit) & 0X6f2cd00000000000(64bit)

0X0000000000023400(64bit) & 0X325da00000000000(64bit)

0X0000000000024500(64bit) & 0X43ffc00000000000(64bit)

this keeps happening and due to the varying data this Page Address/wrong data is going to our module/design as a valid data and is creating problems to our design.

This RX port is of 64 bit width

Is there any way to handle or eliminate this data from being received at the rx port ??

More Info on IP generation

HARD IP is generated for

PHY type - ARRIAII GX

lane - x1

port type - Native Endpoint

Application Interface - Avalon ST 64bit

PCI Express Version - 1.1

maximum payload - 256

desired performance for receiving request - MAXIMUM

BAR REGISTERS

Bar 0 - 32 bit non-prefetchable

Bar 1 - 32 bit non-prefetchable

Bar 2 - 32 bit non-prefetchable