Guidance in designing a Synchronous NAND Flash (ONFI 2.x/Toggle-Mode) interface.
I am looking into the possibility of rolling my own external memory interface (Controller and PHY) to support Synchronous NAND Flash protocols. Either ONFI 2.x (Micron and others) or "Toggle"-mode (Toshiba and others). The Altera target device will be Cyclone V. I have successfully designed for an asynchronous NAND Flash but that was pretty easy. I could go and purchase IP in the market but we have some very special requirements for the controller. The design of the PHY, I hope, can take advantage of Altera's ready-to-go Megafunctions. The trouble is, I need a guide to what Megafunctions I need to use and how best to use them. Although not appropriate since it is for Stratix III and IV, the "External Memory Interface Handbook Vol 5: Section I - Implementing Custom Memory Interface PHY", EMI_CUSTOM-1.1, Dec 2010 is what I am looking for. For those who are not familiar with ONFI 2.x "synchronous" NAND Flash interface, it is spec'ed to "leverage" already familiar DDR techniques.
Thanks, Mark Boston, MA BTW, I am not an "Altera beginner". I guess I need to edit my profile sometime:oops: