New ContributorGuidance for using UART IP if Quartus
I wasn't able to locate guidance of how to generate the UART IP from Quartus, so I followed the process of UART generation, which was fairly simple. There were quite a few files generated, also I was expecting only Verilog files, assuming there is no hard macro inside (see attached).
I assume that UART_inst.v the instantiation, yet where can I see the memory mapped registers that the the verilog design should access when writing data to the UART, or reading from?
Is there a ready made example?
Also, does it make sense to control the UART with pure Verilog code to do the following activities:
- After reset, get a stream of bytes from the host to upload to a memory, and trigger a state machine on the FPGA
- When the activity is done, send few bytes to the host.
Or would it be better to use the NIOS processor to do these activities?
All is documented here: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-3/uart-core.html
The memory map is here: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-3/register-map-38176.html
The _inst.v is an instantiation template, not the actual instantiation. You copy the template into your code and edit it to connect to the rest of your project.
As for your usage, that's up to you. You can use the JTAG UART IP with Nios to send and receive characters while the design is running in hardware for debug.
