Global Variables in VHDL

Global signals and global shared variables have been around since the dawn of VHDL I think (at least since 93). They allow you to put a signal/shared variable in a package. This signal/variable is then accessible/modifiable to all code that use the package.

This feature is only meant as a debugging tool. So much so that altera refuse to compile global signals. They know about them but will not allow their compilation.

Are you sure you're not thinking about accessing things heirarchically? in 2008 you can access signals/variables without having to send them through port maps, but again, its only meant for debugging.