Honored ContributorHi All,
How can I know what pins could be used as the Global, Local, Regional, and Peripheral clocks in the ArriaV device (as an example)? What difference between these clocks? Where to read about (manual/tutorial/userguide)? Thank you!
Honored ContributorHi dmitryl,
As far as I know you can use any pin as global, local, regional or peripheral clock when you use Altera's ATLCLKCTRL IP block. The IP block allows you to "promote" a certain signal to travel over dedicated spines, e.g. the global spine which covers the entire FPGA, or a local clock spine, which covers only certain area of the FGPA etc. Regards, Richard.Honored ContributorCannot find the ATLCLKCTRL IP in the IP-Catalog... I'm using the Quartus-II v15.0. Where should I see for this IP? Thank you
Honored ContributorShould I manually insert this IP into my HDL code?
Honored ContributorWhat's the difference between the Local, Regional, and Peripheral clocks? Are there another clock types (besides Global)?
Honored ContributorIs every device pin/pad has an attached Global Clock Buffer? I had a design where the Fitter went to another rib of the device to pick up a Global Clock buffer there... Why did it do so? How to avoid such route "travelling"?
Honored ContributorProbably the Fitter make such a route to meet timing requirement .
Honored ContributorRead the Clock Networks section of the arria v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/arria-v/av_5v2.pdf). Table 4-1 shows you exactly which pins you should use to access the clock resources available. Avoid specifically instantiating the ALTCLKCTRL IP and let Quartus chose the appropriate resources needed for your design.
Cheers, AlexHonored ContributorGenerally you should only manually assign the clock network type if you have in depth understanding on the clock network and have specific reason ie fanout, timing meeting.
Honored ContributorHonored ContributorThanks to all! It was a mistake of a board designer so he connected a clock source to a pin, which was not a dedicated clock pin. As the result, the fitter traveled to far for just picking up a global clock buffer. This travelling was resulted in the setup violations of about 3(!) clock cycles!
It seems I resolved the issue by switching the "Global Signal" pin attribute to OFF. https://www.alteraforum.com/forum/attachment.php?attachmentid=11546
