glitich in the outputs

This code you have registered your state machine, but the outputs from the state machine are not registered.

Library ieee;
use ieee.std_logic_1164.all;
PORT (Right,Left,Hazard : IN STD_LOGIC;
  Clk, Reset : IN STD_LOGIC;
  LA,LB,LC : OUT STD_LOGIC;
  RA,RB,RC : OUT STD_LOGIC);
END Vehicle_Tail_Lights_control;
ARCHITECTURE state_machine OF Vehicle_Tail_Lights_control IS
  TYPE state_type IS (Idle,L1,L2,L3,R1,R2,R3,LR3);
  attribute ENUM_ENCODING: STRING;
  attribute ENUM_ENCODING of state_type: type is
  "000 001 011 010 101 111 110 100";
  SIGNAL current_state, next_state : state_type;
BEGIN
  
  PROCESS(Clk,Reset,next_state)
  BEGIN
    if (Reset='0') then
      current_state<= Idle;
    elsif (Clk'event AND Clk='1') then
    
      current_state <= next_state;
    end if;
  END PROCESS;
  PROCESS(current_state,Right,Left,Hazard)
  BEGIN
    CASE current_state IS
      WHEN idle =>
        Lc<='0';Lb<='0';La<='0';Ra<='0';Rb<='0';Rc<='0';
        IF ( (Hazard='1') OR ((Left='1') AND (Right='1')))
        THEN next_state <= LR3;
        ELSIF ( (Hazard='0') AND (Left='0') AND (Right='1'))
        THEN next_state <= R1;
        ELSIF ((Hazard='0') AND (Left='1') AND (Right='0'))
        THEN next_state <= L1;
        ELSE
          next_state <= Idle;
        END IF;
          
      WHEN L1 =>
        Lc<='0';Lb<='0';La<='1';Ra<='0';Rb<='0';Rc<='0';
        IF (Hazard = '1') THEN next_state <= LR3;
        ELSE next_state <= L2;
        END IF;
          
      WHEN L2 =>
        Lc<='0';Lb<='1';La<='1';Ra<='0';Rb<='0';Rc<='0';
        IF (Hazard = '1') THEN next_state <= LR3;
        ELSE next_state <= L3;
        END IF;
          
      WHEN L3 =>
        Lc<='1';Lb<='1';La<='1';Ra<='0';Rb<='0';Rc<='0';
        next_state <= Idle;
        
      WHEN R1 =>
        Lc<='0';Lb<='0';La<='0';Ra<='1';Rb<='0';Rc<='0';
        IF (Hazard = '1') THEN next_state <= LR3;
        ELSE next_state <= R2;
        END IF;
          
      WHEN R2 =>
        Lc<='0';Lb<='0';La<='0';Ra<='1';Rb<='1';Rc<='0';
        IF (Hazard = '1') THEN next_state <= LR3;
        ELSE next_state <= R3;
        END IF;
          
      WHEN R3 =>
        Lc<='0';Lb<='0';La<='0';Ra<='1';Rb<='1';Rc<='1';
        next_state <= Idle;
        
      WHEN LR3 =>
        Lc<='1';Lb<='1';La<='1';Ra<='1';Rb<='1';Rc<='1';
        next_state <= idle;
        
    END CASE;
  END PROCESS;
END state_machine;

thank you for the reply, is ent u the codes for my program, i just would like to know how to register my outputs to get rid of the glitches,

how about posting more of yuor code?

could you please let me know how to register my outputs and what is the diffrence between the registerd output and buffered outputs

If the outputs are already registered, the problem is apparently different from simple combitional logic glitches, then it's rather a FSM design problem. You can use SignalTap to trace inputs, state variables an doutputs of the FSM.

yes i do understand , but when i add the clock to the senstivity list in the process the responsible for the outputs, i have to

The sensitivity list in your always statement does not do anything about glitches. You have to do something about either your state assignments or register the output.

i already added the clock to the senstivity list in the process that performs the outputs but i still have the glitches

Standard Mealy or Moore FSM designs, e.g. the Quartus HDL templates don't register the output signals, resulting in glitches. You should register those signals, that are fed to output pins.