Giving external input to Triple Speed Ethernet

Hi,

To generate PRBS packet, LFSR5 is used for 32 bits

but I didn't understand the statement

next_value <= ((((next_value << 5) & 32'hFFFFFFE0) | ((next_value >> 27) & 32'h0000001F)) + 32'h33557799);

in this program:

begin

if(go_bit & !running_bit)

begin

next_value <= initial_value;

end

else if(((state == DATA_STATE) || (state == EOP_STATE)) && aso_src0_valid && aso_src0_ready)

begin

next_value <= ((((next_value << 5) & 32'hFFFFFFE0) | ((next_value >> 27) & 32'h0000001F)) + 32'h33557799);

end

Theory seems to be clear from here

http://www1.verigy.com/cntrprod/groups/public/documents/webcontent/cnsmprod_020300.pdf

but not the program.

could anybody please explain little bit?

You can use whatever RAM you like (on-chip, off-chip, SRAM, SDRAM, etc.).

The RAM is there so that software (by default iniche) has storage for Ethernet frames. The SGDMA controllers transfer the frames between RAM and Avalon-ST (for the TSE ports).

It sounds like you need to change the memory controller to match whatever memory you have in your hardware design.

Hi,

Is it compulsory to use External RAM (and thus DDR2 SDRAM controller) in "udp offload example"? I really don't understand the purpose of it in this project.

If so, is DDR2 SDRAM controller compatible with Quartus Web edition (Free version) and CycloneIVE or there is some kind of licence stuff?

I am asking this because following error occurs on compilation.

Error (292019): Core "DDR2 High Performance Controller" (6AF7_00BF) is not enabled for current device family

Hi,

If I want to give continuous data stream input from ADC (10 bit) to this "UPD Offload example", then where I have to change in this design? I mean at which component?

Yes I recommend to use the CPU, as they do in the offload example. It will make everything easier. IT doesn't need to be very powerful, so even the /e core, that doesn't require a license, can be used.

As long as your hardware module is able to generate UDP packets on the avalon stream at 750Mbps, the TSE should be able to follow. Just check that the CPU configured the TSE and the PHY correctly in gigabit mode first.

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If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers.

It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software,

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Does it mean you are recommending to use CPU to ease the work :)

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even if once initialized you only use hardware to generate or process the packets.

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So, it will be somehow similar to "UDP offload example" recommended by ted. Does it fulfill speed requirement (750Mbps+), if I proceed in this way?

If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers.

It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software, even if once initialized you only use hardware to generate or process the packets.

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Hi,

Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?

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It is definitely possible to make a Qsys design without using a NIOS II processor. The examples all include a NIOS processor because that is what most people do.

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Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?

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The transmit and receive ports are Avalon-ST. You send/receive an Avalon-ST packet containing the Ethernet packet. It's pretty simple. Avalon-ST is described in this document:

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

set_1000 and set_100 are described in the TSE user guide (search for their names and you will see both diagrams and written explanations).

http://www.altera.com/literature/ug/ug_ethernet.pdf

As previously mentioned, you may want to consider working through the UDP Offload example and just keep deleting stuff you don't need until you are able to figure out how everything works as you will learn a lot by having done that exercise.

Hi,

Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?

Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?

The problem is I am not using NIOSII Processor in my design, therefore I need to write some kind of logic in Hardware to control them in order to send continuous data stream and finally integrate them in Qsys as a component.

set_10

set_1000

tse_mac_transmit.data

.endofpacket

.error

.empty

.ready

.startofpacket

.valid

tse_mac_receive.data

.valid

.endofpacket

.empty

.ready

.startofpacket

.error

I have seen some info on online training as below but this is not sufficient as logic is missing there and that is also controlled by NIOSII Processor.

// streaming sink interface (for input data)

output asi_RGBIN_ready,

input asi_RGBIN_valid,

input [31:0] asi_RGBIN_data,

// streaming source interface (for output data)

input aso_XYZOUT_ready,

output aso_XYZOUT_valid,

output [31:0] aso_XYZOUT_data,