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Hi,
Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?
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It is definitely possible to make a Qsys design without using a NIOS II processor. The examples all include a NIOS processor because that is what most people do.
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Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?
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The transmit and receive ports are Avalon-ST. You send/receive an Avalon-ST packet containing the Ethernet packet. It's pretty simple. Avalon-ST is described in this document:
http://www.altera.com/literature/manual/mnl_avalon_spec.pdf set_1000 and set_100 are described in the TSE user guide (search for their names and you will see both diagrams and written explanations).
http://www.altera.com/literature/ug/ug_ethernet.pdf As previously mentioned, you may want to consider working through the UDP Offload example and just keep deleting stuff you don't need until you are able to figure out how everything works as you will learn a lot by having done that exercise.
Honored Contributor
