Giving external input to Triple Speed Ethernet

Hi,

Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?

Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?

The problem is I am not using NIOSII Processor in my design, therefore I need to write some kind of logic in Hardware to control them in order to send continuous data stream and finally integrate them in Qsys as a component.

set_10

set_1000

tse_mac_transmit.data

.endofpacket

.error

.empty

.ready

.startofpacket

.valid

tse_mac_receive.data

.valid

.endofpacket

.empty

.ready

.startofpacket

.error

I have seen some info on online training as below but this is not sufficient as logic is missing there and that is also controlled by NIOSII Processor.

// streaming sink interface (for input data)

output asi_RGBIN_ready,

input asi_RGBIN_valid,

input [31:0] asi_RGBIN_data,

// streaming source interface (for output data)

input aso_XYZOUT_ready,

output aso_XYZOUT_valid,

output [31:0] aso_XYZOUT_data,