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If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers.
It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software,
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Does it mean you are recommending to use CPU to ease the work :)
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even if once initialized you only use hardware to generate or process the packets.
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So, it will be somehow similar to "UDP offload example" recommended by ted. Does it fulfill speed requirement (750Mbps+), if I proceed in this way?
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