Giving external input to Triple Speed Ethernet

The TSE uses two Avalon Stream interfaces for Ethernet packets: a source with received packets and a sink for packets to transmit. Usually in a design with a Nios II CPU and a software layer with a TCP/IP stack, those two interfaces are connected to SGDMAs in QSys. If you do it that way and have the correct software solution, then you can directly send and receive packets through the software API.

If you need a higher bandwidth you can also make your own IP and connect it to the avalon stream interfaces in QSys instead of the DMAs and generate packets directly there.

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Usually in a design with a Nios II CPU and a software layer with a TCP/IP stack, those two interfaces are connected to SGDMAs in QSys. If you do it that way and have the correct software solution, then you can directly send and receive packets through the software API.

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Hi, I didn't get the point: send and receive packets through the software API. which API software can be used in this case?

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If you need a higher bandwidth you can also make your own IP and connect it to the avalon stream interfaces in QSys instead of the DMAs and generate packets directly there.

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yes, I need higher bandwidth 750 Mbps+. In attachment, there is screenshot of how I connect SGDMAs to other components in Qsys. If I remove this SGDMAs, where exactly I have to connect (to the avalon stream interfaces) from own IP.

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If I remove this SGDMAs, where exactly I have to connect (to the avalon stream interfaces) from own IP.

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You would connect to the "transmit" and "receive" Avalon Streaming ports of the TSE MAC.

See this page:

http://www.alterawiki.com/wiki/nios_ii_udp_offload_example

In that example, IP blocks are connected in addition to the SGDMA (through the packet multiplexer/demultiplexer pair).

Replace the "PRBS packet generator", "UDP payload inserter", and "Alignment pad inserter" with your own IP (and same thing on the receive side, if needed).

If you don't need the NIOS / SGDMA, then you probably delete the multiplexer/demultiplexer as well and connect directly to the TSE MAC.

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Hi, I didn't get the point: send and receive packets through the software API. which API software can be used in this case?

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It depends on what you choose to usr as a software platform. The Altera examples use the uCOS II embedded operating system with the Interniche TCP/IP stack. This has a standard bsd sockets api (https://en.wikipedia.org/wiki/bsd_socket) that you can use to send packets from the software. Other developers prefer to use LwIP or Linux.

But you will never be able to generate 750Mb+ traffic with a software solution. You need to generate your packets in hardware, and the offload example indicated by ted is a good starting point.

Yes, you can definitely do it that way (export and manually connect the signals). But my preference is to follow the approach in the UDP offload example, and bundle your IP in Qsys components in order to avoid having to make those connections manually, and to make it easier to build a more complex system in the future.

And yes, you always have to recompile the project if you change something.

Hi,

Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?

Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?

The problem is I am not using NIOSII Processor in my design, therefore I need to write some kind of logic in Hardware to control them in order to send continuous data stream and finally integrate them in Qsys as a component.

set_10

set_1000

tse_mac_transmit.data

.endofpacket

.error

.empty

.ready

.startofpacket

.valid

tse_mac_receive.data

.valid

.endofpacket

.empty

.ready

.startofpacket

.error

I have seen some info on online training as below but this is not sufficient as logic is missing there and that is also controlled by NIOSII Processor.

// streaming sink interface (for input data)

output asi_RGBIN_ready,

input asi_RGBIN_valid,

input [31:0] asi_RGBIN_data,

// streaming source interface (for output data)

input aso_XYZOUT_ready,

output aso_XYZOUT_valid,

output [31:0] aso_XYZOUT_data,

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Hi,

Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?

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It is definitely possible to make a Qsys design without using a NIOS II processor. The examples all include a NIOS processor because that is what most people do.

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Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?

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The transmit and receive ports are Avalon-ST. You send/receive an Avalon-ST packet containing the Ethernet packet. It's pretty simple. Avalon-ST is described in this document:

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

set_1000 and set_100 are described in the TSE user guide (search for their names and you will see both diagrams and written explanations).

http://www.altera.com/literature/ug/ug_ethernet.pdf

As previously mentioned, you may want to consider working through the UDP Offload example and just keep deleting stuff you don't need until you are able to figure out how everything works as you will learn a lot by having done that exercise.

If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers.

It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software, even if once initialized you only use hardware to generate or process the packets.

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If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers.

It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software,

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Does it mean you are recommending to use CPU to ease the work :)

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even if once initialized you only use hardware to generate or process the packets.

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So, it will be somehow similar to "UDP offload example" recommended by ted. Does it fulfill speed requirement (750Mbps+), if I proceed in this way?

Yes I recommend to use the CPU, as they do in the offload example. It will make everything easier. IT doesn't need to be very powerful, so even the /e core, that doesn't require a license, can be used.

As long as your hardware module is able to generate UDP packets on the avalon stream at 750Mbps, the TSE should be able to follow. Just check that the CPU configured the TSE and the PHY correctly in gigabit mode first.