Honored Contributor
Honored ContributorI have used a ready latency of 0 in my modules. The Rx TSE ST has a ready latency of 2 cycles. I used a Avalon ST timing adapter to handle this conversion.
Here is the signal tap output of the RX TSE ST interface when first packet is received. https://www.alteraforum.com/forum/attachment.php?attachmentid=14849 This is the signal tap output of the RX TSE ST interface when another packet is sent. The ready is back at 1, but there are no more valids generated for a long time. While the data (0x0000007) is correct, it doesn't receive a valid for a very long time. I was triggering on startofpacket, and so it didn't capture the packet. If I trigger on Valid, i see the packet received. It is a bit strange though, that it takes a while to send out valid. https://www.alteraforum.com/forum/attachment.php?attachmentid=14850 I have a question regarding the initialization of the TSE MAC. I read that alt_sys_init() calls the component INIT and INSTANCE macros. SO it should call the INIT TSE MAC function. My understanding is that it is called automatically on startup. There need not be a call specified in the application program. Is this correct?
