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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

get_rtl_cells seems returns incomplete list of cells

Dear Forum,

I'm writing script to get list of rtl cells using following scheme:

execute_module -tool map

execute_module -tool fit

set fullcollection [get_rtl_cells -hierarchical -nocase *]

foreach_in_collection cell $cell_list {

set type [get_rtl_cell_info -type $cell]

puts -nonewline $cell

puts -nonewline " - "

puts "[get_rtl_cell_info -name $cell] - type: $type"

}

The resulting output is the following:

cell_0 - Decoder0 - type: DECODER

cell_4 - out - type: MUX

cell_5 - in - type: IO

cell_6 - sel[0] - type: IO

cell_7 - sel[1] - type: IO

cell_8 - out[0] - type: IO

cell_9 - out[1] - type: IO

cell_10 - out[2] - type: IO

cell_11 - out[3] - type: IO

When using Tools->Netlist Viewers->RTL Viewer I have found that there is actually 4 instances of MUX (out~0....out~4). How to get these instances?

Verilog code:

module DeMux_4x2 (in, sel, out);

input in;

input [1:0] sel;

output [3:0] out;

reg [3:0] out;

always @(sel or in)

begin

case(sel)

2'b00: out <= {3'b000, in};

2'b01: out <= {2'b00, in, 1'b0};

2'b10: out <= {1'b0, in, 2'b00};

2'b11: out <= {in, 3'b000};

endcase

end

endmodule

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I'm guessing the RTL "under the hood" is a single mux but the RTL viewer draws it as one per bit. What are you trying to do? I've never used get_rtl_cells or found a reason to and wonder if there's another way.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    I'm guessing the RTL "under the hood" is a single mux but the RTL viewer draws it as one per bit. What are you trying to do? I've never used get_rtl_cells or found a reason to and wonder if there's another way.

    --- Quote End ---

    Actually I'm trying to analyze and understand how the rtl view got constructed by the synthes tool.

    From above example you can see that my verilog is doing simple demux which after syntheses transformed to one decoder and 4 muxes.

    By calling get_rtl_cells I didn't get all instances of the mux, it only gave 1 of them.

    Please note that in the cell-id's there are missing 3 id's for those instances:

    cell_0

    cell_1

    cell_2

    cell_3

    cell_4

    Why I'm not getting cell_1.. cell_3? And how the RTL Netlist View tool in the Quartus determines this?